About

I am a Research Fellow at the University of Bologna, in the PULP Lab, part of the PULP Platform run jointly with ETH Zürich. I work with Prof. Francesco Conti on the deployment of AI workloads on heterogeneous parallel many-core architectures.

I received my M.Sc. in Telecommunications Engineering from the University of Bologna in March 2026. My thesis, Tiny LLM Automatic Deployment for RISC-V-Based High-Efficiency Compute Cluster Platforms, extended the open-source Deeploy compiler so that a small transformer language model runs on an eight-core RISC-V cluster with 128 KiB of scratchpad memory.

Research interests

Hardware–software co-design for edge AI on RISC-V platforms:

• neural-network compilers and the deployment of transformer and small language models;
• cycle-level modelling of heterogeneous many-core and in-memory-computing accelerators;
• embedded system software: device drivers and real-time operating systems.

Open-source work

• Deeploy #153: FP32 operators and tiling support for MicroLlama on Snitch. My thesis work, merged in August 2026 into Deeploy, the compiler jointly maintained by ETH Zürich and the University of Bologna.
• Accelerator Phylogeny. An interactive evolutionary tree of AI accelerators.

More detail is on the CV page.